1. Field of the Invention
The present invention relates to a video signal interface, and in particular to a video signal interface used for an output display of an information processor.
2. Description of the Related Art
Display devices used as display apparatus connected to information processor include CRTs (cathode-ray tubes), LCDs (liquid crystal displays), and plasma displays. It is necessary to vary the format of the image signal that the information processor inputs to the display apparatus in accordance with the type of display device used. Generally, however, the format of the image signal or picture signal sent from the information processor is of one specific type, and as a result, in order to use a display device that is not compatible with the image signal from the information processor, it is necessary to employ an interface that converts the image signal to one that is compatible with the display device to be used.
FIG. 1 is a block diagram showing the composition of an interface for converting image signals outputted by an information processor for use by a color CRT display to signals for use by a monochrome LCD display panel. The LCD panel is used for displaying eight shades of gray. Here, the image signals for use by the color CRT are made up of three color signals (Red, Green, and Blue), a horizontal synchronous signal HSY, a vertical synchronous signal VSY, and a dot clock signal DCK, and each of these signals is inputted to the LCD video signal interface 65. In addition, a reset signal RST is also inputted to the interface 65 in order to reset the interface 65 itself. The data supplied to the LCD panel 68 from the interface 65 is LCD display data signals and LCD display timing signals.
Of the signals making up the image signal for use by a color CRT, the color signals indicate display data used when displaying on a CRT and the remaining HSY, VSY, and DCK signals are used to determine the display timing. Each color signal includes one bit for each pixel and is transmitted as serial data.
This interface 65 is connected to a memory unit 66 made up of three frame buffer memories 67.sub.1 to 67.sub.3. The frame buffer memories 67.sub.1 to 67.sub.3 are for storing in frame units the image appearing on the CRT and store the images for each constituent, red, green and blue.
The LCD video signal interface 65 comprises a timing generating circuit 60 to generate the necessary timing signals, an address generating circuit 61 for generating address signals of the frame memories 67.sub.1 to 67.sub.3 based on the output of the timing generating circuit 60, an S/P converter circuit 59 for converting the serial data of each color signal to parallel data, three bi-directional buffers 64.sub.1 to 64.sub.3 making up part of the interface and corresponding to the three frame buffer memories 67.sub.1 to 67.sub.3, a data latch circuit 62 that acquires data read out from the frame buffer memories 67.sub.1 to 67.sub.3 and synchronizes it with the LCD display timing signal, and a gray-scale pattern data producing circuit 63 that produces 8-toned gray-scale data from the three-element color signals. The timing generating circuit 60 is composed such that it produces a signal for generating addresses, LCD display timing signals, output enable signals OE, and write enable signals WE from the inputted signals HSY, VSY, RST, and DCK. The two enable signals OE and WE are signals for controlling the input and output of the frame buffer memories 67.sub.1 to 67.sub.3.
In this interface 65, the three color signals are each converted into parallel data in the S/P converter circuit 59, and the parallel data is outputted to the frame buffer memories 67.sub.1 to 67.sub.3 by way of the bi-directional buffers 64.sub.1 to 64.sub.3. In accordance with write enable signals WE and address signals, each type of display data expressed in parallel data for each of the colors, red, green and blue, is stored in each of the frame buffer memories 67.sub.1 to 67.sub.3. The data stored in the buffer memories 67.sub.1 to 67.sub.3 is read out based on the address signals and output enable signals OE and inputted to the data latch circuit 62 after being passed through the bi-directional buffer 64.sub.1 to 64.sub.3 and being synchronized with the LCD display timing signal. The display data outputted from the data latch circuit 62 is converted to gray-scale pattern data by means of the gray-scale data generating circuit 63, synchronized with the LCD display timing signal and outputted to the LCD panel 68 as LCD display data.
A one-bit color signal has three components, each color signal may represent 8 (=2.sup.3) colors. Since the gray-scale also consists of eight shades, each color of the display data for the CRT will correspond to one shade among the eight gray-scales in a one-to-one fashion. The correspondence of the colors to the shades is predetermined, and the gray-scale data generating circuit 63 generates the gray-scale pattern data based on this set correspondence.
In this type of interface of the prior art, since the CRT display data is stored as is in the frame buffer memory as color signals, it is necessary to prepare a buffer memory for one screen for each of the colors, red green and blue, with the result that a total of three frame buffer memories are necessary. In addition, there is the disadvantage that, because the correspondence between the colors and the gray-scales is set and unchanging, display data that produces a good image on a CRT will not necessarily produce a good image when converted to data for display on an LCD panel.